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flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 as29f010 rev. 0.3 10/02 128k x 8 flash uniform sector 5.0v flash memory available as military specifications ? mil-std-883 ? smd 5962-96690 features ? single 5.0v 10% power supply operation ? low power consumption: ! 12 ma typical active read current ! 30 ma typical program/erase current ! <1 a typical standby current ? flexible sector architecture ! eight 16kbyte sectors ! any combination of sectors can be erased ! full chip erase ? sector protection ! hardware-based feature that disables/reenables program and erase operations in any combination of sectors ! sector protection/unprotection can be implemented using standard prom programming equipment ? embedded algorithms ! embedded erase algorithm automatically pre-programs and erases the chip or any combination of designated sectors ! embedded program algorithm automatically programs and verifies data at specified address ? erase suspend/resume ! supports reading data from a sector not being erased ? minimum 1 million erase cycles guaranteed per sector ? compatible with jedec standards ! pinout and software compatible with single-power- supply flash ! superior inadvertent write protection ? data\ polling and toggle bits ! provides a software method of detecting program or erase cycle completion options marking ? timing 50ns* -5 60ns -6 70ns -7 90ns -9 120ns -12 150ns -15 ? package ceramic dip (600 mil) cw ? temperature industrial temperature (-40c to +85c) it military temperature (-55c to +125c) xt 883c processing (-55c to +125c) 883c qml processing (-55c to +125c) q notes: *50ns (-5) option available with it, xt, and 883c options only. for more products and information please visit our web site at www.austinsemiconductor.com pin assignment (top view) 32-pin ceramic dip (cw) nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss v cc we\ nc a14 a13 a8 a9 a11 oe\ a10 ce\ dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 as29f010 rev. 0.3 10/02 general description the as29f010 is a 1mbit, 5.0 volt-only flash memory organized as 131,072 bytes. the as29f010 is offered in a 32-pin cdip package. the byte-wide data appears on dq0-dq7. the device is designed to be programmed in-system with the standard system 5.0 volt v cc supply. a 12.0 volt v pp is not required for program or erase operations. the device can also be programmed or erased in standard eprom programmers. this device is manufactured using 0.32 m process technology. it is available with access times of 50, 60, 70, 90, 120, and 150ns, allowing high-speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce\), write enable (we\), and output enable (oe\) controls. the device requires only a single 5.0 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this invokes the embedded program algorithm -- an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. device erasure occurs by executing the erase command sequence. this invokes the embedded erase algorithm -- an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by reading the dq7 (data\polling) and dq6 (toggle) status bits. after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is erased when shipped from the factory. the hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory, and is implemented using standard eprom programmers. the system can place the device into the standby mode. power consumption is greatly reduced in this mode. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection. pin configuration pin description a0 - a16 17 addresses dq0 - dq7 8 data inputs/outputs ce\ chip enable oe\ output enable we\ write enable v cc +5 vold single power supply v ss device ground nc no connect logic symbol
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 as29f010 rev. 0.3 10/02 functional block diagram
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 as29f010 rev. 0.3 10/02 device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is composed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the appropriate device bus operations table lists the inputs and control levels required, and the resulting output. the following subsections describe each of these operations in further detail. requirements for reading array data to read array data from the outputs, the system must drive the ce\ and oe\ pins to v il . ce\ is the power control and selects the device. oe\ is the output control and gates array data to the output pins. we\ should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read operations table for timing specifications and to the read operations timings diagram for the timing waveforms. icc1 in the dc characteristics table represents the active current specification for reading array data. table 1: device bus operations operation ce\ oe\ we\ addresses 1 dq0 - dq7 read l l h a in d out write l h l a in d in standby v cc 0.5v x x x high-z output disable l h h x high-z hardware reset x x x x high-z notes: 1. addresses are a16:a0. 2. the sector protect and sector unprotect functions must be implemented via programming equipment. see the ?sector protection / unprotection? section. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we\ and ce\ to v il , and oe\ to v ih . an erase operation can erase one sector, multiple sectors, or the entire device. the sector address tables indicate the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. see the ?command definitions? section for details on erasing a sector or the entire chip. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7 - dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? and ?autoselect command sequence? sections for more information. i cc2 in the dc characteristics table represents the active current specification for the write mode. the ?ac characteristics? section contains timing specification tables and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7 - dq0. standard read cycle timings and i cc read specifications apply. refer to ?write operation status? for more information, and to each ac characteristics section in the appropriate data sheet for timing diagrams.
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 as29f010 rev. 0.3 10/02 standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe\ input. the device enters the cmos standby mode when the ce\ pin is held at v cc 0.5v. (note that this is a more restricted voltage range than v ih .) the device enters the ttl standby more when ce\ is held at v ih . the device requires the standard access time (t ce ) before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. output disable mode when the oe\ input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7 - dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins a6, a1, and a0 must be as shown in the autoselect codes (high voltage method) table. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining sector a16 a15 a14 address range sa0 0 0 0 00000h - 03fffh sa1 0 0 1 04000h - 07fffh sa2 0 1 0 08000h - 0bfffh sa3 0 1 1 0c000h - 0ffffh sa4 1 0 0 10000h - 13fffh sa5 1 0 1 14000h - 17fffh sa6 1 1 0 18000h - 1bfffh sa7 1 1 1 1c000h - 1ffffh table 2: sector addresses table note: all sectors are 16 kbytes in size. address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7 - dq0 to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see ?command definitions? for details on using the autoselect mode. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection/unprotection must be implemented using programming equipment. the procedure requires a high voltage (v id ) on address pin a9 and the control pins. the device is shipped with all sectors unprotected. it is possible to determine whether a sector is protected or unprotected. see ?autoselect mode? for details. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the command definitions table). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 as29f010 rev. 0.3 10/02 erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5ns (typical) on oe\, ce\, or we\ do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe\ = v il , ce\ = v ih or we\ = v ih . to initiate a write cycle, ce\ and we\ must be a logical zero while oe\ is a logical one. power-up write inhibit if we\ = ce\ = v il and oe\ = v ih during power up, the device does not accept commands on the rising edge of we\. the internal state machine is automatically reset to reading array data on power-up. command definitions writing specific address and data commands or sequences into the command register initiates device operations. the command definitions table defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we\ or ce\, whichever happens first. refer to the appropriate timing diagrams in the ?ac characteristics? section. table 3: autoselect codes (high voltage method) description ce\ oe\ we\ a16 to a14 a13 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq7 to dq0 manufacturer id l l h x x v id xlxll 01h device id l l h x x v id xlxlh 20h 01h (protected) 00h (unprotected) lxhl sa x v id x sector protection verification llh note: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see the ?reset command? section, next. see also ?requirements for reading array data? in the ?device bus operations? section for more information. the read operations table provides the read parameters, and the read operation timings diagram shows the timing diagram. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data. once programming begins, however, the device ignores reset com- mands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data. if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data.
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 as29f010 rev. 0.3 10/02 autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this method is an alternative to that shown in the autoselect codes (high voltage method) table, which is intended for prom programmers and requires v id on address bit a9. the auto select command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h or retrieves the manufacturer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refer to the sector address tables for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. byte program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verify the programmed cell margin. the command definitions take shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. see ?write operation status? for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may halt the operation and set dq5 to ?1?, or cause the data\ polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1?. chip erase command sequence chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. the system can determine the status of the erase operation by using dq7 or dq6. see ?write operation status? for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 2 illustrates the algorithm for the erase operation. see the erase/program operations tables in ?ac characteristics? for parameters, and the chip /sector erase operation timings for timing waveforms. note: see the appropriate command definitions table for program command sequence. figure 1: program operation
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 as29f010 rev. 0.3 10/02 sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the addresss of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50s begins. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50s, the system need not monitor dq3. any command during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the ?dq3: sector erase timer? section.) the time-out begins from the rising edge of the final we\ pulse in the command sequence. once the sector erase operation has begun, all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6. refer to ?write operation status? for information on these status bits. figure 2 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the ?ac characteristics? section for parameters, and to the sector erase operations timing diagram for timing waveforms. erase suspend/erase resume commands the erase suspect command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50s time-out period during the sector erase note: 1) see the appropriate command definitions table for program command sequence. 2) see ?dq3: sector erase timer? for more information. figure 2: erase operation command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspect command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are ?don?t cares? when writing the erase suspect command. when the erase suspect command is written during a sector erase operation, the device requires a maximum of 20s to suspend the erase operation. however, when the erase suspect command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspected, the system can read array data from any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on dq7-dq0. the system can use dq7 to determine if a sector is actively erasing or is erase-suspended. see ?write operation status? for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 as29f010 rev. 0.3 10/02 non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see ?autoselect command sequence? for more information. the system must write the erase resume command (address bits are ?don?t care?) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. table 4: command definitions addr data addr data addr data addr data addr data addr data 1ra rd 1 xxxx f0 3 555 aa 2aa 55 555 f0 manufacturer id 4 555 aa 2aa 55 555 90 x00 1 device id 4 555 aa 2aa 55 555 90 x01 20 0 1 4 555 aa 2aa 55 555 a0 pa pd 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 1 xxx b0 1 xxx 30 55 555 90 (sa) x02 4 555 aa 2aa erase resume 10 read 4 reset 6 sector protect verify 8 pro g ram chip erase sector erase erase suspend 9 reset 5 autoselect 7 cycles bus cycles 2,3 first second third fourth fifth sixth command sequence 1 legend: x = don?t care ra = address of the memory location to be read rd = data read from location ra during read operation pa = address of the memory location to be programmed. addresses latch on the falling edge of the we\ or ce\ pulse, whichever h appens later pd = data to be programmed at location pa. data latches on the rising edge of we\ or ce\ pulse, whichever happens first sa = address of the sector to be verified (in autoselect mode) or erased. address bits a16-a14 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all command bus cycles are write operations. 4. no unlock or command cycles required when reading array data. 5. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (wh ile the device is providing status data). 6. the device accepts the three-cycle reset command sequence for backward compatibility. 7. the fourth cycle of the autoselect command sequence is a read operation. 8. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more inform ation. 9. the system may read in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspen d command is valid only during a sector erase operation. 10. the erase resume command is valid only during the erase suspend mode.
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 as29f010 rev. 0.3 10/02 write operation status the device provides several bits to determine the status of a write operation: dq3, dq5, dq6, and dq7. table 5 and the following subsections describe the functions of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data\ polling the data\ polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or completed. data\ polling is valid after the rising edge of the final we\ pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data\ polling on dq7 is active for approximately 2s, then the device returns to reading array data. during the embedded erase algorithm, data\ polling produces a ?0? on dq7. when the embedded erase algorithm is complete, data\ polling produces a ?1? on dq7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to ?1?; prior to this, the device outputs the ?complement,? or ?0?. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data\ polling on dq7 is active for approximately 100s, then the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7-dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0-dq6 while output enable (oe\) is asserted low. the data\ polling timings (during embedded algorithms) figure in the ?ac characteristics? section illustrates this. table 5 shows the outputs for data\ polling on dq7. figure 3 shows the data\ polling algorithm. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete. toggle note: 1) va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2) dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 3: data\ polling algorithm bit i may be read at any address, and is valid after the rising edge of the final we\ pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. (the system may use either oe\ or ce\ to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 as29f010 rev. 0.3 10/02 selected for erasing are protected, dq6 toggles for approximately 100s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. if a program address falls within a protected sector, dq6 toggles for approximately 2s after the program command sequence is written, then returns to reading array data. the write operation status table shows the outputs for toggle bit i on dq6. refer to figure 4 for the toggle bit algorithm, and to the toggle bit timings figure in the ?ac characteristics? section for the timing diagram. reading toggle bit dq6 refer to figure 4 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7-dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7-dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit it toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 4). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. note: 1) read toggle bit twice to determine whether or not it is toggling. see text. 2) recheck toggle bit because it may stop toggling as dq5 changes to ?1?. see text. figure 4: toggle bit algorithm
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 as29f010 rev. 0.3 10/02 dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from ?0? to ?1.? the system may ignore dq3 if the system can guarantee that the time between additional sector erase commands will always be less than 50s. see also the ?sector erase command sequence? section. after the sector erase command sequence is written, the system should read the status on dq7 (data\ polling) or dq6 (toggle bit i) to ensure the device has accepted the command sequence, and then read dq3. if dq3 is ?1?, the internally controlled erase cycle has begun; all further commands are ignored until the erase operation is complete. if dq3 is ?0?, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 5 shows the outputs for dq3. table 5: write operation status notes: 1. dq7 requires a valid address when reading status information. refer to the appropriate subsection for further details. 2. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. see ?dq5: exceeding timing limits? for more information. dq7 1 dq6 dq5 2 dq3 embedded program algorithm dq7\ toggle 0 n/a embedded erase algorithm 0 toggle 0 1 reading within erase suspended sector 1 no toggle 0 n/a reading within non-erase suspended sector data data data data standard mode erase suspend mode operation *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. absolute maximum ratings* ambient temperature with power applied............-55c to +125c voltage with respect to ground v cc 1 .................................................................-2.0v to +7.0v a9 2 ................................................................-2.0v to +13.0v all other pins 1 ...............................................-2.0v to +7.0v output short circuit current 3 ..................................................200ma v cc supply voltage..................................................+4.50v to +5.50v storage temperature..................................................-65c to +125c notes: 1. minimum dc voltage on input or i/o pin is -0.5v. during voltage transitions, input may overshoot v ss to -2.0v for periods of up to 20ns. see figure 5. maximum dc voltage on input and i/o pins is v cc + 0.5v. during voltage transitions, input and i/o pins may overshoot v cc + 2.0v for periods up to 20ns. see figure 6. 2. minimum dc voltage on a9 pin is -0.5v. during voltage transitions, a9 pins may overshoot v ss to -2.0v for periods of up to 20ns. see figure 5. maximum dc input voltage on a9 is +12.5v which may overshoot to 14.0v for periods up to 20ns. 3. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. figure 5: maximum negative overshoot waveform figure 6: maximum positive overshoot waveform
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 13 as29f010 rev. 0.3 10/02 dc characteristics: ttl/nmos compatible parameter description sym min typ max unit input load current v in = v ss to v cc , v cc = v cc max i li 5.0 a a9 input load current v cc = v cc max, a9 = 12.5v i lit 100 a output leakage current v out = v ss to v cc , v cc = v cc max i lo 5.0 a v cc active read current 1,2 ce\ = v il , oe\ = v ih i cc1 12 35 ma v cc active write current 2,3,4 ce\ = v il , oe\ = v ih i cc2 30 50 ma v cc standby current ce\ and oe\ = v ih i cc3 0.4 5.0 ma input low voltage v il -0.5 0.8 v input high voltage v ih 2.0 v cc + 0.5 v voltage for autoselect and sector protect v cc = 5.0v v id 10.5 12.5 v output low voltage i ol = 12 ma, v cc = v cc min v ol 0.45 v output high voltage i oh = -2.5 ma, v cc = v cc min v oh 2.4 v low v cc lock-out voltage v lko 3.2 v notes: 1. the i cc current listed is typically less than 2ma/mhz, with oe\ at v ih . 2. maximum i cc specifications are tested with v cc = v cc max 3. i cc active while embedded program or embedded erase algorithm is in progress. 4. not 100% tested. dc characteristics: cmos compatible parameter description sym min typ max unit input load current v in = v ss to v cc , v cc = v cc max i li 5.0 a a9 input load current v cc = v cc max, a9 = 12.5v i lit 50 a output leakage current v out = v ss to v cc , v cc = v cc max i lo 5.0 a v cc active current 1,2 ce\ = v il , oe\ = v ih i cc1 35 ma v cc active current 2,3,4 ce\ = v il , oe\ = v ih i cc2 50 ma v cc standby current ce\ = v cc 0.5v, oe\ = v ih i cc3 1.6 ma input low voltage v il -0.5 0.8 v input high voltage v ih 0.7 x v cc v cc + 0.3 v voltage for autoselect and sector protect v cc = 5.25v v id 10.5 12.5 v output low voltage i ol = 12 ma, v cc = v cc min v ol 0.45 v i oh = -2.5 ma, v cc = v cc min v oh1 0.85 v cc v i oh = -100 a, v cc = v cc min v oh2 v cc - 0.4 low v cc lock-out voltage v lko 3.2 v output high voltage
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 14 as29f010 rev. 0.3 10/02 table 6: test conditions, test specifications conditions all speeds unit output load output load capacitance, c l (including jig capacitance) 50 pf input rise and fall times 5 ns input pulse levels 0/3 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v 1 ttl gate ac characteristics: read-only operations figure 7: test conditions, test setup jedec std -50 -60 -70 90 -120 -150 read cycle time 1 t avav t rc min50607090120150ns address to output delay t avqv t acc ce\ = v il oe\ = v il max 50 60 70 90 120 150 ns chip enable to output delay t elqv t ce oe\ = v il max 50 60 70 90 120 150 ns output enable to output delay t glqv t oe max 25 30 35 40 50 55 ns chip enable to output high z 1 t ehqz t df max 15 20 20 25 30 35 ns output enable to output high z 1 t ghqz t df max 15 20 20 25 30 35 ns read min ns toggle and data polling min ns output hold time from addresses ce\ or oe\, whichever occurs first t axqx t oh min ns parameter test setup output enable hold time 1 t oeh symbol units 0 10 0 speed options notes: 1. not 100% tested. 2. see figure 7 and table 6 for test specifications.
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 15 as29f010 rev. 0.3 10/02 figure 8: ac characteristics, read operations timings ac characteristics: erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. jedec std -50 -60 -70 90 -120 -150 write cycle time 1 min t avav t wc 50 60 70 90 120 150 ns address setup time min t avwl t as ns address hold time min t wlax t ah 40 45 45 45 50 50 ns data setup time min t dvwh t ds 25 30 30 45 50 50 ns data hold time min t whdx t dh ns output enable setup time min t oes ns read recover time before write (oe\ high to we\ low) min t ghwl t ghwl ns ce\ setup time min t elwl t cs ns ce\ hold time min t wheh t ch ns write pulse width min t wlwh t wp 25 30 35 45 50 50 ns write pulse width high min t whwl t wph ns byte programming operation 2 min t whwh1 t whwh1 s chip/sector erase operation 2 max t whwh2 t whwh2 sec v cc set up time 1 min t vcs s symbol parameter units 0 0 0 speed options 0 0 0 20 14 60 50
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 16 as29f010 rev. 0.3 10/02 figure 9: ac characteristics, program operation timings notes: pa = program address, pd = program data, d out is the true data at the program address. figure 10: ac characteristics, chip/sector erase operation timings notes: sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status).
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 17 as29f010 rev. 0.3 10/02 figure 11: data\ polling timings (during embedded algorithms) notes: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 12: ac characteristics, toggle bit timings (during embedded algorithms) notes: va = valid address, not required for dq6. illustration shows first two status cycle after command sequence, last status read c ycle, and array data read cycle.
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 18 as29f010 rev. 0.3 10/02 ac characteristics: erase and program operations jedec std -50 -60 -70 90 -120 -150 write cycle time 1 min t avav t wc 50 60 70 90 120 150 ns address setup time min t avel t as ns address hold time min t elax t ah 40 45 45 45 50 50 ns data setup time min t dveh t ds 25 30 30 45 50 50 ns data hold time min t ehdx t dh ns output enable setup time 1 min t oes ns read recover time before write min t ghel t ghel ns we\ setup time min t wlel t ws ns we\ hold time min t ehwh t wh ns ce\ pulse width min t eleh t cp 25 30 35 45 50 50 ns ce\ pulse width high min t ehel t cph ns byte programming operation 2 min t whwh1 t whwh1 s chip/sector erase operation 2 typ t whwh2 t whwh2 sec 20 14 60 symbol parameter units 0 0 0 speed options 0 0 0 notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. figure 13: ac characteristics, alternate ce\ controlled write operation timings notes: 1. pa = program address, pd = program data, sa = sector address, dq7\ = complement of data input, d out = array data. 2. figure indicates the last two bus cycles of the command sequence.
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 19 as29f010 rev. 0.3 10/02 erase and programming performance typ 1 max 2 unit chip/sector erase time 1.0 15 sec excludes 00h programming prior to erasure 4 byte programming time 7 300 s chip programming time 3 0.9 6.25 sec parameter limits comments excludes system-level overhead 5 notes: 1. typical program and erase times assume the following conditions: 25c, 5.0v v cc , 1 million cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 4.5v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes progr am faster than the maximum byte program time listed. if the maximum byte program time given is exceeded, only then does the device set d q5 = 1. see the section on dq5 for further information. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the four-but-cycle command sequence for programming. see table 4 for further information on command definitions. 6. the device has a minimum guaranteed erase cycle endurance of 1 million cycles. latchup characteristic parameter min max input voltage with respect to v ss on i/o pins -1.0v v cc + 1.0v v cc current -100ma +100ma notes: includes all pins except v cc . test conditions: v cc = 5.0v, one pin at a time. pin capacitance parameter conditions symbol max unit input capacitance v in = 0 c in 15 pf output capacitance v out = 0 c out 15 pf control pin capacitance v pp = 0 c in2 15 pf notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz data retention parameter co nditions min unit 150c 10 years 125c 20 years minimum pattern data retention time
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 20 as29f010 rev. 0.3 10/02 mechanical definitions* package designator c *all measurements are in inches. min max a 0.140 0.202 a1 0.190 0.047 a2 0.125 0.193 b 0.009 0.012 b1 0.590 0.610 d 1.654 1.686 d1 0.580 0.604 d2 1.492 1.508 e 0.095 0.105 e1 0.016 0.020 symbol asi specifications
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 21 as29f010 rev. 0.3 10/02 *available processes xt = military temperature range -55 o c to +125 o c it = industrial temperature range -40c to +85c 883c = 883c processing -55c to +125c q = qml processing -55c to +125c **note: 50ns (-5) option available with it, xt, and 883c options only. ordering information example: as29f010cw-9/883c device number package type speed ns process as29f010 cw -5** /* as29f010 cw -6 /* as29f010 cw -7 /* as29f010 cw -9 /* as29f010 cw -12 /* as29f010 cw -15 /*
flash flash flash flash flash as29f010 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 22 as29f010 rev. 0.3 10/02 asi to dscc part number cross reference* asi package designator cw asi part # smd part # as29f010cw-6/q 5962-9669005hya as29f010cw-7/q 5962-9669004hya as29f010cw-9/q 5962-9669003hya as29f010cw-12/q 5962-9669002hya as29f010cw-15/q 5962-9669001hya * asi part number is for reference only. orders received referencing the smd part number will be processed per the smd.

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